1. Technical Field of the Invention
The present invention relates generally to the field of integrated circuits and, more particularly, to oscillator delay cells.
2. Description of Related Art
Controlled ring oscillators are common building blocks in most communication systems, especially in applications such as phase locked loops, clock generations and clock distributions. The frequency of operation, jitter or phase noise, tuning range and frequency stability with temperature, supply voltage variation are typical characteristics which must be considered when designing oscillators. Differential ring oscillators, in particular, offer a key advantage of being integratable on a chip without external components, which becomes very important for applications where space is very limited. LC oscillator or crystal oscillators generally provide low jitter or phase noise, but also generally require external chip components. Some disadvantages of typical CMOS differential ring oscillators include a relatively lower phase noise performance and the increased sensitivity to supply voltage change when compared to LC oscillator or a crystal oscillator.
In general, a differential ring oscillator is comprised of several cascaded stages of identical differential delay cells connected in such a manner as to provide an effective phase inversion allowing oscillation. Typically, these stages are used to provide the instability and feedback necessary for oscillation. The amount of jitter or phase noise in a ring oscillator is determined by the nature of the differential delay cells and the biasing tail currents, particularly in a low power application. To reduce the overall jitter and phase noise of a ring oscillator, care must be taken to ensure that each differential delay cell contributes minimal noise. Furthermore, the device noise of each tail current transistor is also a considerable source of jitter, particularly, in extra low power applications.
Therefore, there is a need for a differential delay cell which reduces or eliminates phase, jitter, and/or flicker noise for use in ring oscillators, PLL, DLL, and other communication systems, in low power applications.
The present invention achieves technical advantages as a circuit for providing a symmetrical signal to a communication system which can be integrated in oscillator type circuits, for example. In one embodiment, the circuit includes a pair of half circuits having respective inputs for receiving a differential signal pair, and a pair of symmetry circuits coupled to the half circuits and advantageously configured to provide an output signal exhibiting a symmetrical waveform in response to the received differential input signal. The circuit further enables current steering to each half circuit to advantageously reduce voltage variation on a common node, hence, reducing current fluctuation from a current source.